1. Field of the Invention
The present invention relates to a data multiplexing apparatus for forming a system stream from an audio stream and a video stream.
2. Description of the Related Art
There are known data processing systems for transferring and storing various data that are adapted to multiplex an audio stream and a video stream into a system stream before they are transferred or stored.
Generally, a data processing system is constructed by an encoder unit and a decoder unit that are connected with each other by way of a communication network. The encoder unit generates an audio stream from audio input data and a video stream from video input data, and then multiplexes them into a system stream and transmits it. The decoder unit receives the system stream and demultiplexes it to the audio stream and the video stream and then reproduces audio output data and video output data.
Also, the encoder unit is constructed by an audio encoder that produces an audio stream and a video encoder that produces a video stream. They are connected respectively to an audio stream first-in first-out (FIFO) memory and a video stream FIFO memory which are commonly connected to a single multiplexer. Further, the multiplexer is connected to a header FIFO memory as part of an external memory.
The multiplexer includes an address generation circuit and a selector circuit. The address generation circuit is connected to the above-mentioned three FIFO memories, which are in turn connected to the selector circuit. The selector circuit is also connected to a system clock counter.
Thus, the encoder unit can convert an audio stream and a video stream into a system stream, and transfer it to the decoder unit. Also, the encoder unit can insert a system clock signal showing the current time into the system stream, so that the decoder unit can reproduce the audio stream and the video stream at respective appropriate timings. This will be explained later in detail.
However, the encoder unit stores the audio stream and the video stream and various headers respectively in a plurality of the external FIFO memories. Therefore, a complex interface is required between the encoder unit and each of the FIFO memories which increases the size of the encoder unit and hinders the attempt to realize a down-sized encoder unit with and improved productivity.